Low energy digital circuit design using sub-threshold operation

Scaling of process technologies to smaller dimensions has become a given in the solid-state circuits industry. Recently, process scaling has produced a number of engineering obstacles. Most notably, both active and leakage power of processors are increasing exponentially with technology scaling. For emerging low power applications such as distributed micro-sensor networks or medical applications, low energy operation is the primary concern instead of performance, with the eventual goal of harvesting energy from the environment. Sub-threshold operation has emerged as a promising approach to these ultra-low-energy applications because it achieves the minimum energy per operation. Lowering VDD decreases active energy by VDD. For circuits whose leakage energy becomes comparable to the active energy, an optimum VDD for minimum energy operation exists. This optimum typically occurs in the sub-threshold region [1]. Previous work confirms that sub-threshold operation is functional and that it provides minimum energy operation [1][2]. Several key problems remain that prevent sub-threshold designs from becoming a competitive option. Specifically, it is essential to understand how the minimum energy point depends on different key parameters and to model it for easy application to generic designs. To this end, we have developed a model for determining the optimum point for minimizing energy [3]. We have also analyzed the impact of sizing for minimum energy in sub-threshold circuits [4]. To increase the attractiveness of sub-threshold design, we proposed a method for integrating it with high performance applications to extend DVS across orders of magnitude of frequency variation and verified ultraDVS with a test chip [5]. Figure 1 shows the measured energy profile of the test chip, and Figure 2 shows the die photograph. We are continuing to examine sub-threshold design, focusing on SRAM design in the presence of process variation.